The present invention relates to a semiconductor device, and more particularly to a semiconductor device which has a fin transistor formed to reduce standby leakage current and increase driving current, and a method for manufacturing the same.
As the design rule of below 100 nm is applied for fabricating semiconductor devices, decreased channel length and width and increased doping concentration of a junction region of a transistor cause the junction leakage current to increase due to the increased number of electric fields. Then, it is difficult to achieve the threshold voltage demanded in a highly integrated semiconductor device by utilizing a transistor having the conventional planar channel structure, and there are limitations in improving the refresh characteristic of the semiconductor device.
Thus, a transistor having a three-dimensional channel structure has been studied in an effort to increase the channel length. A fin transistor is one type that has a three-dimensional channel structure. To form a fin transistor, a fin pattern having a projecting active region is formed by recessing an isolation layer, and a gate is then formed to cover the fin pattern. In the fin transistor, the short channel effect can be suppressed due to lowering of the drain induced barrier lowering (DIBL), and a current drive characteristic can be significantly improved since the channels are formed on all three exposed surfaces of the active region.
However, the conventional fin transistor has problems in that the standby leakage current increases since the threshold voltage is decreased. In order to cope with the problems due to the increased standby leakage current, a method for adopting a negative word line has been suggested. Nevertheless, this method is not practical for actual practice due to complicated manufacturing procedures and complex circuitry of the semiconductor device and also due to the increased power consumption of the semiconductor device.
Further, the conventional fin transistor has problems due to decreasing driving current as the integration degree of a semiconductor device increases. One way proposed to solve the problems due to decreasing driving current is to increase the height of the fin pattern. However, more defects are produced by increasing the height of the fin pattern as follows.
First, as a process for forming an isolation layer, a flowable insulation layer such as a spin-on glass (SOG) oxide layer is filled in the lower end of a trench, and an high density plasma (HDP) oxide layer is formed on the SOG oxide layer in order to improve the gap-fill capability for trenches. In this case, increasing the height of a fin pattern leads to the increased loss of an isolation layer, and the loss of the isolation layer would lead to the exposure of the SOG oxide layer, which has a high wet etch rate, thereby degrading the isolation characteristics of the semiconductor device.
Second, increasing the height of the fin pattern may lead to poor etching performance in a subsequent gate forming process, by which the gates may be short-circuited leading to a device failure.
Thus, to address the above-described problems associated with high integration of semiconductor devices, there is a need to reduce the standby leakage current of a transistor and to increase the driving current at the same height of the fin pattern and with the same threshold voltage.